Technical Lead I

October 18, 2021October 18, 2021 | | 0 Comment | 12:30 am

Java – Technical lead (Sr Systems Analyst)

As a Senior Developer/Technical lead, you will

  • Work with Pharmacy Business and IT stakeholders (including architecture group) on design and build/develop of technology solutions of the PBM spectrum 
  • Participate in activities related to the design, development and maintenance of the PBM technology solutioning and enterprise initiatives 
  • Leading or assisting application solution design and build/develop/validate of technical solutions 
  • Creating or updating technical documentation from functional documentation 
  • Works on major projects that may span a broad range of applications 
  • Work with Business SME, Technical Analysts and Architects to come up with solutions and work actively with team members to deliver projects on time and under budget 
  • Expertise in multiple technical environments and possesses business knowledge that spans one or more business areas 
  • Advises and recommends enterprise architecture strategies, processes and methodologies 
  • Shares best practices, lessons learned and constantly updates the technical system architecture requirements based on changing technologies, and knowledge related to recent, current and upcoming vendor products and solutions. 

 

Requirements

  • 7+ years expertise in Core Java
  • 3+ years expertise in Spring Framework
  • 2+ Years Spark
  • Experience working on implementing Accum systems for Major PBMs/ Health care companies is a must
  • Accumes domain knowledge
  • Must have good analysis and problem-solving skills.
  • Should be aware of the industry best practices
  • Knowledge of latest technologies.
  • Work experience in Agile (Scrum) development teams required
  • Experience leading multilocation teams 

 

Role Proficiency:

Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision

 

Outcomes:

  1.   Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
  2.   Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams
  3.   On time quality delivery approved by the project manager and client
  4.   Automate the design tasks flows and write scripts to generate reports
  5.   Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client

 

Measures of Outcomes:

  1.   Quality –verified using relevant metrics by UST Manager / Client Manager
  2.   Timely delivery – verified using relevant metrics by UST Manager / Client Manager
  3.   Reduction in cycle time cost using innovative approaches
  4.   Number of papers published
  5.   Number of patents filed
  6. Number of mandatory trainings attended adhering to training goals

 

Outputs Expected:

Quality of the deliverables:

  1. Ensure zero bugs are present in the design / circuit design.
  2. Clean delivery of the design/module in-terms of ease in integration at the top level
  3. Meeting functional spec / design guidelines 100% without any deviation or limitation
  4. Documentation of tasks and work performed

 

Timely delivery:

  1. Ensure project timelines as laid out by the client or program manager are met
  2. Meet intermediate tasks delivery for other team members to progress
  3. Calling out for help and support in the case of delay in tasks delivery

 

New Skills development:

  1. Participate in training – skilling someone and also getting skilled in newer technologies
  2. Take up new areas of project development learn on the job and deliver

 

Team Work:

  1. Participation in team work and supporting team members at the time of need
  2. Able to take up additional tasks in-case of any team member(s) not available
  3. Able to hand hold junior team members to explain the project tasks and support to deliver
  4. Work dedication to go beyond the call of duty to ensure deadlines and quality are met

 

Innovation & Creativity:

  1. Approach towards repeated work by automating tasks to save design cycle time
  2. Participation on technical discussion training forum white paper etc

 

Skill Examples:

  1.   Languages and Programming skills:a.  System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice
  2.   EDA Tools: a.  Cadence Synopsys Mentor tool sets (one or more)b.  Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools)
  3.   Technical Knowledge:a.  IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb.  Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec.  Strong Physical Design / Circuit Design / Analog Layout Knowledged.  Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione.  Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design
  4.   Technology: CMOS FinFet FDSOI – 28nm / 22nm / 16ff / 10nm and below
  5.   Strong communication skills and ability to interact with team members and clients equally
  6.   Strong analytical reasoning and problem-solving skills with attention to details
  7.   Ability to understand the standard specs and functional documents
  8.   Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT
  9.   Well versed with the available EDA tools and able to use them efficiently
  10.   Required technical skills and prior design knowledge to execute the assigned tasks
  11. Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project

 

Knowledge Examples:

 
Additional Comments:

None

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