SummaryPosted: Oct 15, 2021Role Number: 200301451The cellular RFIC team architects, designs, and validates radio transceivers integrated into complex cellular SoCs.
We invite you to join us, if you are a self-motivating, passionate electrical engineer with RF design and modeling experience.
You will own the RF Integrity of complex cellular transceivers.
This includes identifying coupling concerns, and coordinating with the modeling and RF IC design teams.
You will become part of a hands-on development team that fosters engineering excellence, creativity and innovation.
Collaboration across teams is a key component of success at Apple
– we hope you will thrive in this type of environment.Key Qualifications3 years of working experience in RFIC or RF circuit beyond graduate school studies.Familiar with RFIC design, layout and simulation in Cadence environment.Working knowledge of mobile product and/or RFIC crosstalk and desense problems.
The ability to simplify complex RFIC layouts to identify problems and solutions at early stages of design.Strong fundamentals in 3D/2D EM simulation tools and transmission line theory.Experience with RF lab equipment, such as VNA, real-time scope, spectrum analyzer, radio communication tester, and RF.
diagnostic chamber.Strong academic training and knowledge on fundamentals of SI Signal integrity and PI power integrity issues is a plus.Deep understanding on wireless transceiver designs, architecture and effect of coupling mechanisms on key RF performance indicators, and integration is preferred.Understand how to model the power grid and power network and help predicting the transient and noise effects on the power grid to key RF performance indicators.Familiar with RF impairment from block to transceiver level, including amplifier, filter and PLL.
as well as knowledge on Communication Theory.
Basic understanding for QAM, OFDM, MIMO, etc is a plus.Description
– You will collaborate with the RFIC design, layout, RF architecture and RF integrity modeling teams.
– You will identify victim and aggressor pairs, set coupling specs and understand the impact on overall system performance.
– You will prioritize the tasks and create plans to model and simulate top items.
– You will debug issues and guide layout to improve on chip and on module coupling.
– You will take part in the lab testing of coupling conditions by proposing lab experiments, writing test plans, taking measurements, and analyzing lab data.Education & ExperienceMaster’s degree in Electrical Engineering or related field, and Ph.D.
is preferred.Additional Requirements