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Job Description Central Products Group (CPG) is seeking Design Verification Engineer, who can provide technical leadership and contribution on Verification of Network-on-Chip (NoC) and high-speed Memory Controller IPs.
The individual will help architect, develop and use simulation and/or formal based verification environments, at block and full-chip level, to prove the functional correctness of Network-on-Chip (NoC), System-level Quality of Service (QoS) and DDR, LPDDR, HBM, RLD, and QDR, Memory Controller IP designs.
Your experience and expertise in developing advance SystemVerilog and UVM based testbench and Automation that can scale with Full-Chip will enable improved quality and execution The individual will also collaborate with Architecture, Design, and Software teams to prove that the system-level architecture requirements are met as part of Pre-Si Functional Verification.
Work includes Test Planning, testbench architecture, execution, tracking, coverage closure, and delivery to programs.
Job Qualifications Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.
The ideal candidate is one who has a proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS requirements.
Requires strong understanding of AXI protocol, NoC architecture, DRAM memory controllers, especially DDR4/5, LPDDR4/5, and HBM2/2E/3.
Requires BS w/ 6 yrs or MS w/ 4 yrs or PhD w/ 2 yrs in Electrical Engineering, Computer Engineering or Computer Science.
Requires experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify Full-Chip FPGA designs and memory controller IPs.
Requires strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
Requires familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
Experience with FPGA programming and software is a plus.
Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
Experience with silicon debug at the tester and board level is a plus.
Requisition Numbe r: 153555 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here .
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