Project Overview:
The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to driven the internal components and send data.
Overall Responsibilities:
As a FPGA/ASIC Design Verification Engineer, you will own functional verification for a custom controller. You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the verification effort.
In this role, you will develop test plans for functional units and subsystems. You will analyze coverage from various dimensions and develop monitors and checkers for better quality assurance. In the final stages, you will also run GLS related simulations.
Top 3 Daily Responsibilities:
- UVM/python test development for driving VIPs and other stimulus drivers
- Generation of test components such as monitors, scoreboards and python models
- Coverage closure and GLS bringup and testing
Mandatory Skills/Qualifications: (All skills, both technical and soft, required to be successful in the role)
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
- Experience developing and maintaining verification testbenches, test cases, and test environments.
- Experience in all aspects of verification life cycle, specifically, SDF and GLS simulations
- Experience in ethernet and SPI required
Non-Essential Skills/Qualifications: (Skills that would be nice to have but are not essential in the role)
- Master’s degree in Electrical Engineering, Computer Science, or related field.
- UVM/System verilog experience 5+ years (10 + years preferred
- High proficiency in python
- Knowledge of general purpose operating systems such as Linux and Android.
- Experience in assertions and formal verification preferred
- Experience in ethernet, SPI, AXI, JTAG preferred
- Experience in analog and real number modeling preferred
The target hiring compensation range for this role is $74.01 to $82.24 an hour. Compensation is based on several factors including, but not limited to education, relevant work experience, relevant certifications, and location.
About Aquent Talent:
Aquent Talent connects the best talent in marketing, creative, and design with the world’s biggest brands.
Our eligible talent get access to amazing benefits like subsidized health, vision, and dental plans, paid sick leave, and retirement plans with a match. We also offer free online training through Aquent Gymnasium. More information on our awesome benefits!
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