Experienced Analog Mixed-Signal Layout Design Engineer

Job Description

At Boeing, we innovate and collaborate to make the world a better place. From the seabed to outer space, you can contribute to work that matters with a company where diversity, equity and inclusion are shared values. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.

We are Boeing Research & Technology (BR&T): Boeing’s global research and development team creating and implementing innovative technologies that make the impossible possible and enable the future of aerospace.  We are engineers and technicians, skilled scientists and bold innovators: join us and put your passion, determination, and skills to work building the future!   #TheFutureIsBuiltHere  #ChangeTheWorld

Within BR&T, Boeing’s Solid State Electronics Development organization (SSED) performs microelectronics technology development for aerospace systems.  SSED develops digital, analog, and RF Systems on Chip (SoCs) for radar, navigation, electronic warfare, communications, processing, and other electronic functions. These systems are used on Boeing airborne, terrestrial, and satellite platforms. Designs are implemented with state-of-the-art semiconductor process technologies including CMOS, GaAs, GaN, and SiGe. SSED uses external wafer fabrication services but executes the whole design flow in-house (architecture definition, circuit design, RTL, synthesis, physical layout, verification, packaging and testing).  SSED owns numerous microelectronics projects, funded both by internal Boeing programs and external U.S. Government Science and Technology (S&T) customers. SSED’s large staff of microelectronics engineers conducts research and designs microelectronics hardware in support of these projects.

We are seeking Experienced Analog Mixed-Signal Layout Design Engineer of deep sub-micron CMOS circuits. Experience implementing analog layouts to achieve tight matching, low noise, and low power consumption. Layouts may include analog or digital blocks, resistors, and capacitors, pad IOs, ESD structures, SRAM leaf cells, etc.

This position will sit out either Mountain View CA, El Segundo CA, Huntington Beach CA, Annapolis Junction MD, or Fairfax VA.

This position is hybrid. This means that the selected candidate will be required to perform some work onsite at one of the listed location options.  This is at the hiring team’s discretion and could potentially change in the future.

This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.

Position Responsibilities:

  • Proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly

  • Understanding of IR drop, RC delay, electro migration, self-heating and coupling capacitance management techniques

  • Proficiency in physical verification including DRC, LVS, and ERC, Support parasitic extraction and analysis

  • Scripting skills are considered a plus

  • Good communication skills and ability to work with a cross-functional team

  • Experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits

  • Experience implementing analog layouts to achieve optimized matching for low cross talk and reduced parasitic. Layouts may include analog blocks like op-amps, passive such as resistors, capacitors, pad IOs, ESD structures, etc.

  • Experience in custom and standard cell based floor-planning and hierarchical layout assembly

  • Must understand techniques for managing IR drop, RC delay, electron-migration, self- heating and coupling capacitance

  • Must be able to recognize failure prone circuit and layout structures, have experience in applying DFM best practices, and proactively work with circuit designers to identify the best approach to solving problems

  • High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports

  • Knowledge of CADENCE, MENTOR GRAPHICS and other relevant layout tools

  • Scripting skills in PERL or SKILL are considered a plus, but not required

  • Excellent communication skills and can do approach with cross-functional teams

  • Working closely with the IC design team on layout floor planning and implementation to product finalization

  • From component level layout up to top-level chip assembly 

  • Verification including DRC, LVS, and ERC

  • Support parasitic extraction and analysis

  • Drive continued improvement of layout practices and procedures

  • Self-motivated—requiring minimal supervision

Basic Qualifications (Required Skills/Experience):

  • Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry

  • 4+ years experience working with analog/mixed-signal/digital circuits

Preferred Qualifications (Desired Skills/Experience):

  • Experience developing and calibration of CMOS transistor models for digital, mixed-signal/analog, and RF integrated circuit applications

  • Experience with industry standard EDA tools from Cadence, Mentor, and Synopsys

  • Standard cell development experience and/or familiarity with structured, pitched, or arrayed layout

  • Experience in layout of FinFET technologies

  • Experience with performance analog and high-power layout techniques

  • Experience exercising and debugging the IC verification flow (DRC, LVS, XOR, PEX, etc.)

  • Demonstrated experience in successfully tapeouts of production IC’s

Typical Education/Experience:  Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years’ related work experience or an equivalent combination of technical education and experience (e.g. PhD+4 years’ related work experience, Master+7 years’ related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Relocation: This position offers relocation based on candidate eligibility.

Drug Free Workplace: Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.

Shift Work Statement: This position is for 1st shift.

At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent.  Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.  

The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.  

The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.

Please note that the salary information shown below is a general guideline only.  Salaries are based upon candidate experience and qualifications, as well as market and business considerations.  

Summary pay range min-max: $128,000 – $173,000



Export Control Requirements: U.S. Government Export Control Status: This position must meet export control compliance requirements. To meet export control compliance requirements, a “U.S. Person” as defined by 22 C.F.R. §120.15 is required. “U.S. Person” includes U.S. Citizen, lawful permanent resident, refugee, or asylee.

Export Control Details: US based job, US Person required

Equal Opportunity Employer:

Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.

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