As a successful member of our Diversified Analog Solutions (DAS) Business Unit, you will possess a full understanding of electromagnetics and RF circuits, and be a driven, committed team player.
Our team reports into an Engineering Sr.
Manager and is responsible for designing and simulating all passive aspects of front-end modules including output matching networks, integrated passive devices, thermal simulation, filter design and coupling analysis all under the ever-present constraint of minimizing package size.
Primary Responsibilities: You will be responsible for the development of LNA circuits and multi-chip modules for the wireless infrastructure applications.
Work with a variety of technologies including pHEMT, GaAs HBT, and SOI.
Knowledge of PA and switch is a plus.
You will face challenging tasks in order to meet critical performance parameters in the design of state-of-the-art LNAs.
Hands on design responsibilities include architecture study, circuit design, EM/thermal simulation, IC layout, verification, and production ramp support.
Good knowledge and understanding of laminate, wire bonding, packages, and SMT components.
Expertise in on-die and in-module RF coupling mechanisms, isolation techniques and shielding methods is required.
Support customer related issues and responses as needed.
You must be able to work well with other design engineers, system engineers, IC layout designers, and MCM module designers.
Job Requirements: Bachelors degree with minimum 5 years-experience in IC design or MS/Ph.D with 3 years-design experience.
RFIC Design/simulation expertise with ADS and Cadence tools.
Demonstrated expertise with major EM tool for full IC Module level simulation.
Strong knowledge of RF circuit architectures and design tradeoffs such as LNA’s, PA’s, and Switches.
Experience with LNA/PA matching techniques, device bias design techniques and fundamentals of RF circuit design.
Working knowledge of IC layout techniques & considerations in a Cadence Virtuoso environment.
History of delivering production products and familiarity with key stages in the product development process.
Experienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on RFIC Strong understanding of packaging techniques such as wire bonding (single chip and multi-chip packages) and flip-chip technologies for RF products and their impacts on design Experience with Smith chart, load and source pulling, RF matching, transmission lines in both simulation and lab environment Layout experience using the Cadence flow, including LVS and DRC.
Ability to work with CAD engineers and provide guidance on RF layouts Knowledgeable of all RF parameters such as stability, return loss, harmonics, IMD, P1dB, NF, switching speed, IIP2/3, and ability to design and optimize for each parameter Strong hands on experience of lab equipment including RF signal generators, oscilloscopes, spectrum analyzer, power sensors, and VNAs is required Ability to generate clear technical presentations and data summaries.