In this position, you will be working alongside a World-class SoC System on a Chip design team within the Silicon Engineering Group SEG delivering next-generation Xeon products and related IPs for Server markets.
You will perform all aspects of the SoC design flow from high-level block design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Your responsibilities will include but not be limited to: Block-level floor planning Logic synthesis of design blocks Formal Equivalence Verification FEV Auto Place-and-Route APR using Synopsys ICC tools Timing verification using Synopsys Prime-Time as well as Intel tools Physical verification Layout vs.
Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Manufacturability checks DFM Assist in the preparation of the layout design database for introduction to manufacturing Qualifications Must have a or in Electrical Engineering, Computer Engineering, or Computer Science.
Minimum 5 of with strong VLSI design knowledge, circuit design knowledge, Synthesis, Place-Route optimization, backend electrical tool convergence including timing convergence and layout cleanup and scripting.
Additional Preferred Qualifications: RTL/Logic design Verilog, VCS, etc.
Electronic Design Automation tools, flows and methodology ICCDP, Design Compiler, IC Compiler/ICC, Primetime, VCS, Verilog Layout cleanup expertise DRCs, density, ipc, etc.
Circuit design Computer architecture TCL, Perl and/or C++ programming Strong analytical ability, problem solving and communication skills Ability to work independently and at various levels of abstraction