Pay rate: $ 85/hr on W2Job Title: Information Technology
– Network Engineer 5Duration:6MonthsLocation: Lowell, MassachusettsJob Description:TOP SKILLS:
– Verilog/ VHDL Coding
– FPGA or ASIC
– Traffic Management or other communication coding
– Data Communications or Telecom experiencePrincipal FPGA Design Engineer in Lowell, MADuties:As a member of our FPGA engineering team in the Broadband Access product line, this role will be instrumental in the design, implementation and integration of RTL for Remote Phy (RxD) cable and Passive Optical Network (PON) products.We work as a multi-disciplinary engineering team on groundbreaking products that delivers high speed connectivity to communications companies around the world.Our engineers collaborate with peers across many engineering fields on the design of outstanding programmable logic based wireline solutions.Our FPGA Engineers participate with hardware, software, and test engineers in bring up, design verification test and end-to-end integration of the final product.As a key member of the advanced area of PON, we will look to you for developing digital interfaces in RxD products, supporting the hardware team on circuit board development, writing FPGA code and supporting thermal simulations/estimations in collaboration with mechanical and electrical engineering team members.Will be encouraged to work with the engineers from other sites on joint designs and to share the best design practices and tools.Qualifications:
•Bachelor’s degree in Electronic Engineering/ Computer Science with 12 years of proven experience OR Master’s in Electronic Engineering / Computer Science and eight years of validated experience
•Expertise in implementing designs with Verilog &/ or VHDL languages and completing ASIC or FPGA Xilinx and/or Intel designs.
Ability to find and correct bugs during simulation, lab and customer deployments as needed.
Experience working in a revision-controlled (E.g.
ClearCase) environment.
•Recent hands-on experience in successfully completing development from concept through production and field deployment in one or multiple FPGAs/ ASICs.
•Responsibility for key parts of the design with traffic management/ scheduling design experience a key advantage.Nice to have:Communication sector experience or knowledge.
Some experience in verification for example with System Verilog and Synopsys UVM.
Ability to write scripts.Comments for Suppliers: On-site to start
– hybrid/remote after ramp up