The Silicon Design group is a diverse team of world class silicon engineers.
We have 100 years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware.
We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges.
We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users.
We are involved in all aspects of chip design from definition and architecture through to verification and signoff.
Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
Whether at our Silicon Design Center in Phoenix or at one of our other locations you will get to collaborate and innovate with the world’s leading product development companies.
In our dynamic fast-paced environment you will get to make the impossible possible.
Accenture is invested in our team member’s growth and provide many opportunities for training and skills expansion.
Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, static timing analysis,power analysis,IR Drop, EM, in advanced technology nodes Resolvepowerissues related to physical design, identify potentiallow powersolutions, drive executionandmethodologyimprovements Performcomprehensivepower analysisin vector and vector-less modesof ASIC SoC design Here’s what you need:
– Bachelor’s Degree or equivalent work experience (12 years) or an Associate’s Degree with 8 years of work experience.
-Minimum of years of experience in the following: RTL2GDSIIon advanced technology nodes (7nm andbelow) Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF.
Powerconstraintsgeneration and validation, power analysis, interface with power integrityanalysis tools.
TCL,Pythonand/or Perl programming.EDA tools like DesignCompiler/Genus,Primetime/PrimePower,ICC2/Innovus, Redhawk/Voltus Bonus Points If: Experience runningpower analysisin vector and vector-less modesand achieving optimal QoR on low power designs Knowledge of static timing analysis, power analysisand concepts, defining timingand powerconstraints exceptions,switching activitydefinitionsand simulation vectors Experience withpowerintegrity analysisat block level or top level,including EM, IR & ESDanalysis,power reduction techniquesinSOC design As required by Colorado law under the Equal Pay for Equal Work Act, Accenture provides a reasonable range of compensation for roles that may be hired in Colorado.
Actual compensation is influenced by a wide array of factors including but not limited to skill set, level of experience, and specific office location.
For the state of Colorado only , the range of starting pay for this role is {{$119,880-$227,600}} and information on benefits offered is here.
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