The Data Center Platform Architecture Integration and Validation (PAIV) team is looking for a Memory Validation Architect to join their dynamic and growing organization.
At Intel, we are building new and exciting memory technologies to drive innovation in the datacenter.
That requires us to bring in new Technical Leaders who can steer us to success and help build new products with these technologies.
You will bring your broad understanding of multiple system areas and interfaces with Architecture, Design, and pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on die debug features.
The scope of the deliverable will vary based on the target platform and specific issue at hand.
Hence you must have a solid big picture across the System.
In this role, you will be responsible for: Creating, defining, and developing the system validation environment and test plans.
Use and apply emulation and platform level tools and techniques to ensure performance to spec.
Validation, enablement, and debugging of current and upcoming Memory technologies on server products.
Development of methodologies, execution of validation plans, and debug of failures.
Qualifications You must possess the minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Education Requirements Bachelors degree or higher in Electrical Engineering, Computer Engineering, or a related discipline.
Minimum Qualifications 5 years’ experience in the following areas: Platform Debug, Stability, MTBF, Validation methodologies Memory architecture Silicon and/or platform validation Preferred Qualifications Experience with BIOS/Firmware and silicon debug Experience with X86 and/or systems architecture