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Senior Staff Synthesis and Timing Engineer Description AMD Xilinx is seeking a Sr Staff Synthesis and Timing engineer to participate in the development of large SOC’s with multiple physical blocks and 300 clock domains.
As a ‘Middle End Design” engineer (MED), the candidate will be responsible for the development of complex multi-mode / multi-corner / multi-block SDC files compatible with both front end and back end flows.
He/She will also work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows.
Prior experience developing complex TCL scripts in the DC & PT environment is essential.
Also essential is a deep understanding of various synthesis and timing methodologies and their tradeoffs.
The candidate will also drive the pre-route timing QC and QoR clean up to eliminate SDC issues and ensure a quality SDC handoff for both pre-route and post-route use.
He/She will need to support the RTL design team in the RTL handoff process by running additional QC regressions including LINT, DFT DRC, CDC, RDC, CLP, and Fishtail.
The candidate will be responsible for driving content owners and managing the overall RTL dashboard cleanup for each RTL handoff milestone.
As a senior member of the team, the candidate will be expected to mentor junior engineers and contribute to the overall technical growth of the MED organization.
Where required, the candidate will also be expected to serve as a technical lead guiding and driving other members on the project, both inside and outside of the organization.
High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits are encouraged to apply.
Experience With The Following Is Required Synopsys: Design Compiler (Logic Synthesis) Synopsys: Primetime (STA) Experience With Any Of The Following Is Desired Synopsys: Spyglass RTL LINT Synopsys: Spyglass RTL DFT Mentor: Questa CDC (Zero In) Mentor: Questa RDC Cadence: Conformal Low Power Fishtail: Confirm Shell Scripting Experience Proficient with scripting languages TCL, Perl, Python, CSH Proficient with Cron and LSF job control automation Experience And Education Bachelor’s degree or equivalent with 8 years of experience, or a master’s degree with 6 years of experience.
Location: San Jose, CA Requisition Numbe r: 162901 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here .
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